The present invention relates to a method of fabricating a semiconductor memory device. More particularly, the present invention relates to a method of fabricating a stacked capacitor using electroplating.
As the integration of dynamic random access memories (DRAMs) has increased, methods have been proposed for thinning a dielectric film of a capacitor to increase capacitance within a limited cell area, or for changing the structure of a capacitor lower electrode to a three-dimensional structure to increase the effective area of a capacitor.
However, even though these methods have been adopted, it is difficult to obtain a sufficient capacitance for device operation in 1-Gbit or greater DRAM memory devices using an existing dielectric. In order to solve the above problem, research has actively pursued methods for replacing the dielectric film of a capacitor with a thin film having a high dielectric constant, such as (Ba,Sr)TiO.sub.3 (BST), PbZrTiO.sub.3 (PZT), and (Pb,La)(Zr,Ti) (PLZT) films.
In conventional devices, when a high dielectric material such as BST is used in a DRAM, a buried contact (BC) is initially formed by a conductive plug such as doped polysilicon. An electrode material is then deposited to form a lower electrode, and the dielectric material is deposited, thereby fabricating the lower portion of a capacitor.
In the capacitor using the above-described high dielectric film such as a BST film, a platinum-group element or an oxide thereof, e.g., Pt, Ir, Ru, RuO.sub.2, or IrO.sub.2, is used as an electrode material. However, Pt, which has an excellent oxidation-resistant property, is greatly reactive with silicon. Hence, when the platinum-group elements, such as Pt, or their oxides are employed as an electrode material, a BC and a lower electrode will react with each other and mutually diffuse when the electrode material contacts the doped polysilicon that forms the BC.
Thus, in a conventional method of fabricating a capacitor, a barrier layer for separating the BC from the lower electrode must be formed between these two layers to prevent mutual reaction and diffusion from occurring between them.
However, when a barrier layer is formed between the BC and the lower electrode, oxygen may diffuse and enter into the sidewalls of the barrier layer during the formation of a dielectric layer. As a result, the conventional technique requires a special process for forming spacers to cover the sidewalls of a barrier layer, in order to prevent oxygen from diffusing through the sidewalls of a barrier layer. Consequently, the capacitor fabricating process is complicated.
Also, in the conventional technique, in order to form a lower electrode using a platinum-group metal as an electrode material, a conductive layer is formed of the platinum-group metal, and is then patterned by dry etching to form a storage node. However, the conductive layer formed of the platinum-group metal is very difficult to dry etch. As a result, when forming memory devices that have a storage node of 300 nm or less in width, particularly in 4-Gbit or more DRAMs, there is a limit in forming a lower electrode by dry etching.